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XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
? Logic 0 = No transmit FIFO reset (default).
? Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
? Logic 0 = Normal Operation (default).
? Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level. Table 10 shows the complete selections. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
T ABLE 10: T RANSMIT AND R ECEIVE FIFO T RIGGER T ABLE AND L EVEL S ELECTION
T RIGGER
T ABLE
FCTR
B IT -5
FCTR
B IT -4
FCR
B IT -7
FCR
B IT -6
FCR
B IT -5
FCR
BIT -4
R ECEIVE
T RIGGER L EVEL
T RANSMIT
T RIGGER
L EVEL
C OMPATIBILITY
Table-A
0
0
0
0
1 (default)
16C550, 16C2550,
0
0
1
1
0
1
0
1
1 (default)
4
8
14
16C2552, 16C554,
16C580
Table-B
0
1
0
0
16
16C650A
0
1
1
1
0
1
8
24
30
0
0
1
1
0
1
0
1
24
8
16
24
28
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